VLSI Design and Embedded Systems

VLSI Design and Embedded Systems CHAPTER 1 INTRODUCTION 1.1 Motivation Phase locked loop (PLL) [1-3] is the heart of the many modern electronics as well as communication system. Recently plenty of the researches have conducted on the design of phase locked loop (PLL) circuit and still research is going on this topic. Most of the researches have conducted to realize a higher lock range PLL with lesser lock time [4] and have tolerable phase noise. The most versatile application of the phase locked loops (PLL) is for clock generation and clock recovery in microprocessor, networking, communication systems, and frequency synthesizers. Phase locked-loops (PLLs) are commonly used to generate well-timed on-chip clocks in high-performance digital systems. Modern wireless communication systems employ Phase Locked Loop (PLL) mainly for synchronization, clock synthesis, skew and jitter reduction [5]. Phase locked loops find wide application in several modern applications mostly in advance communication and instrumentation systems. PLL being a mixed signal circuit i nvolves design challenge at high frequency. Since its inspection in early 1930s, where it was used in the synchronization of the horizontal and vertical scans of television, it has come to an advanced form of integrated circuit (IC). Today found uses in many other applications. The first PLL ICs were available around 1965; it was built using purely analog component. Recent advances in integrated circuit design techniques have led to the development of high performance PLL which has become more economical and reliable. Now a whole PLL circuit can be integrated as a part of a larger circuit on a single chip. There are mainly five blocks in a PLL. These are phase frequency detector (PFD), charge pump (CP), low pass loop filter (LPF), voltage controlled oscillator (VCO) and frequency divider. Presently almost all communication and electronics devices operate at a higher frequency, so for that purpose we need a faster locking PLL. So there are a lot of challenges in designing the mentioned different blocks of the PLL to operate at a higher frequency. And these challenges motivated me towards this research topic. In this work mainly the faster locking of the PLL is concentrated by properly choosing the circuit architectures and parameters. The optimization of the VCO circuit is also carried out in this work to get a better frequency precision. 1.2 Organization of Thesis Before going into the details of the PLL, the motivation behind this work is mentioned in the Chapter 1 of the thesis. Chapter 2 briefly describes the whole PLL system. An introduction to the PLL circuit is mentioned in the section 2.1. Section 2.2 contains the detail architecture of the whole PLL system. Different types of PLLs are mentioned in the section 2.3. Section 2.4 explains the basic terms used in the PLL system while the consecutive sections give the details about the noise and application of the PLL. Chapter 3 builds the concepts of optimization. Definition of optimization technique and different circuit optimization techniques are presented in section 3.1 and 3.2 respectively. Section 3.3 gives the brief outline of the concept of geometric programming and convex optimization. The optimization of the CSVCO circuit is explained in section 3.4. The design and synthesis of the PLL is described in Chapter 4. The different design environments used in this work is mentioned in the section 4.1. The adopted design procedure is explained in section 4.2. Section 4.3 gives the design specifications and parameters of the work. The simulation results of the different circuits used in the PLL are depicted in the different sections of the Chapter 5. The performance of the CSVCO designed using convex optimization is compared with that of the traditional method in section 5.3. Section 5.5 gives the different simulation results of the PLL and its performance comparison between schematic and post layout level. At last Chapter 6 provides the conclusion that inferred from the work. CHAPTER 2 PHASE LOCKED LOOP 2.1 Introduction A PLL is a closed-loop feedback system that sets fixed phase relationship between its output clock phase and the phase of a reference clock. A PLL is capable of tracking the phase changes that falls in this bandwidth of the PLL. A PLL also multiplies a low-frequency reference clock CKref to produce a high-frequency clock CKout this is known as clock synthesis. A PLL has a negative feedback control system circuit. The main objective of a PLL is to generate a signal in which the phase is the same as the phase of a reference signal. This is achieved after many iterations of comparison of the reference and feedback signals. In this lock mode the phase of the reference and feedback signal is zero. After this, the PLL continues to compare the two signals but since they are in lock mode, the PLL output is constant. The basic block diagram of the PLL is shown in the Figure 2.1. In general a PLL consists of five main blocks: Phase Detector or Phase Frequency Detector (PD or PFD) Charge Pump (CP) Low Pass Filter (LPF) Voltage Controlled Oscillator (VCO) Divide by N Counter The â€Å"Phase frequency Detector† (PFD) is one of the main parts in PLL circuits. It compares the phase and frequency difference between the reference clock and the feedback clock. Depending upon the phase and frequency deviation, it generates two output signals â€Å"UP† and â€Å"DOWN†. The â€Å"Charge Pump† (CP) circuit is used in the PLL to combine both the outputs of the PFD and give a single output. The output of the CP circuit is fed to a â€Å"Low Pass Filter† (LPF) to generate a DC control voltage. The phase and frequency of the â€Å"Voltage Controlled Oscillator† (VCO) output depends on the generated DC control voltage. If the PFD generates an â€Å"UP† signal, the error voltage at the output of LPF increases which in turn increase the VCO output signal frequency. On the contrary, if a â€Å"DOWN† signal is generated, the VCO output signal frequency decreases. The output of the VCO is then fed back to the PFD in or der to recalculate the phase difference, and then we can create closed loop frequency control system. 2.2 PLL Architecture The architecture of a charge-pump PLL is shown in Figure 2.2. A PLL comprises of several components. They are (1) phase or phase frequency detector, (2) charge pump, (3) loop filter, (4) voltage-controlled oscillator, and (5) frequency divider. The functioning of each block is briefly explained below. 2.2.1 Phase Frequency Detector The â€Å"Phase frequency Detector† (PFD) is one of the main part in PLL circuits. It compares the phase and frequency difference between the reference clock and the feedback clock. Depending upon the phase and frequency deviation, it generates two output signals â€Å"UP† and â€Å"DOWN†. Figure 2.3 shows a traditional PFD circuit. If there is a phase difference between the two signals, it will generate â€Å"UP† or â€Å"DOWN† synchronized signals. When the reference clock rising edge leads the feedback input clock rising edge â€Å"UP† signal goes high while keeping â€Å"DOWN† signal low. On the other hand if the feedback input clock rising edge leads the reference clock rising edge â€Å"DOWN† signal goes high and â€Å"UP† signal goes low. Fast phase and frequency acquisition PFDs [6-7] are generally preferred over traditional PFD. 2.2.2 Charge Pump and Loop Filter Charge pump circuit is an important block of the whole PLL system. It converts the phase or frequency difference information into a voltage, used to tune the VCO. Charge pump circuit is used to combine both the outputs of the PFD and give a single output which is fed to the input of the filter. Charge pump circuit gives a constant current of value IPDI which should be insensitive to the supply voltage variation [8]. The amplitude of the current always remains same but the polarity changes which depend on the value of the â€Å"UP† and â€Å"DOWN† signal. The schematic diagram of the charge pump circuit with loop filter is shown in the Figure 2.4. When the UP signal goes high M2 transistor turns ON while M1 is OFF and the output current is IPDI with a positive polarity. When the down signal becomes high M1 transistor turns ON while M2 is OFF and the output current is IPDI with a negative polarity. The charge pump output current [3] is given by IPDI=IPUMP—IPUMP4Ï€Ãâ€"ΔÎ ¦ =2IPUMP4Ï€Ãâ€"ΔÎ ¦ =IPUMP2Ï€Ãâ€"ΔÎ ¦ =KPDIÃâ€"ΔÎ ¦ (1) Where KPDI=IPUMP2Ï€ (amps/radian) (2) The passive low pass loop filter is used to convert back the charge pump current into the voltage. The filter should be as compact as possible [9].The output voltage of the loop filter controls the oscillation frequency of the VCO. The loop filter voltage will increase if Fref rising edge leads Fin rising edge and will decrease if Fin rising edge leads Fref rising edge. If the PLL is in locked state it maintains a constant value. The VCO input voltage is given by Vinvco = KF Ãâ€" IPDI (3) Where KF is the gain of the loop filter. 2.2.3 Voltage Controlled Oscillator An oscillator is an autonomous system which generates a periodic output without any input. The most popular type of the VCO circuit is the current starved voltage controlled oscillator (CSVCO). Here the number of inverter stages is fixed with 5. The simplified view of a single stage current starved oscillator is shown in the Figure 2.5. Transistors M2 and M3 operate as an inverter while M1 and M4 operate as current sources. The current sources, Ml and M4, limit the current available to the inverter, M2 and M3; in other words, the inverter is starved for current. The desired center frequency of the designed circuit is 1GHz with a supply of 1.8V. The CSVCO is designed both in usual manner as mentioned in [3], [10, 11]. The general circuit diagram of the current starved voltage controlled oscillator is shown in the Figure 2.6. To determine the design equations for the CSVCO, consider the simplified view of VCO in Figure 2.5. The total capacitance on the drains of M2 and M3 is given by Ctot=52Cox(LpWp+LnWn) (4) The time it takes to charge Ctot from zero to VSP with the constant current ID4 is given by t1=VSPID4Ãâ€"Ctot (5) While the time it takes to discharge Ctot from VDD to VSP is given by t1=VDD-VSPID1Ãâ€"Ctot (6) If we set ID4= ID1=ID then the sum of t1 and t2 is given by t1+t2=VDDIDÃâ€"Ctot (7) The oscillation frequency of CSVCO for N number of stage is fosc=1Nt1+t2=IDNCtotVDD (8) This is equal to fcenter when Vinvco=VDD2 (9) The gain of the VCO is given by KVCO=fmax-fminVmax-Vmin HzV (10) 2.2.4 Frequency Divider The output of the VCO is fed back to the input of PFD through the frequency divider circuit. The frequency divider in the PLL circuit forms a closed loop. It scales down the frequency of the VCO output signal. A simple D flip flop (DFF) acts as a frequency divider circuit. The schematic of a simple DFF based divide by 2 frequency divider circuit is shown in the Figure 2.7. 2.3 Types of PLL There are mainly 4 types of PLL are available. They are . Liner PLL Digital PLL All Digital PLL Soft PLL 2.4 Terms in PLL 2.4.1 Lock in Range Once the PLL is in lock state what is the range of frequencies for which it can keep itself locked is called as lock in range. This is also called as tracking range or holding range. 2.4.2 Capture Range When the PLL is initially not in lock, what frequency range can make PLL lock is called as capture range. This is also known as acquisition range. This is directly proportional to the LPF bandwidth. Reduction in the loop filter bandwidth thus improves the rejection of the out of band signals, but at the same time the capture range decreases, pull in time becomes larger and phase margin becomes poor. 2.4.3 Pull in Time The total time taken by the PLL to capture the signal (or to establish the lock) is called as Pull in Time of PLL. It is also called as Acquisition Time of PLL. 2.4.4 Bandwidth of PLL Bandwidth is the frequency at which the PLL begins to lose the lock with reference. 2.5 Noises in PLL The output of the practical system deviates from the desired response. This is because of the imperfections and noises in the system. The supply noise also affects the output noise of the PLL system [12]. There are mainly 4 types of noises. They are explained below. 2.5.1 Phase Noise The phase fluctuation due to the random frequency variation of a signal is called as phase noise. This is mostly affected by oscillators frequency stability. The main sources of the phase noise in PLL are oscillator noise [12-15], PFD and frequency divider circuit. The main components of the phase noise are thermal and flicker noise. 2.5.2 Jitter A jitter is the short term-term variations of a signal with respect to its ideal position in time [16-19]. This problem negatively impacts the data transmission quality. Jitter and phase noise are closely related and can be computed one from another [18]. Deviation from the ideal position can occur on either leading edge or trailing edge of signal. Jitter may be induced and coupled onto a clock signal from several different sources and is not uniform over all frequencies. Excessive jitter can increase bit error rate (BER) of communication signal [19]. In digital system Jitter leads to violation in time margins, causing circuits to behave improperly. 2.5.3 Spur Non-desired frequency content not related to the frequency of oscillation and its harmonics is called as â€Å"Spur†. There are mainly two types of spur. They are reference spur and fractional spur. Reference spur comes into picture in an integer PLL while fractional spur plays a major role in fractional PLL. When the PLL is in lock state the phase and frequency inputs to the PFD are essentially equal. There should not be any error output from the PFD. Since this can create problem, so the PFD is designed such that, in the locked state the current pulses from the CP will have a very narrow width as shown in the Figure 2.9. Because of this the input control voltage of the VCO is modulated by the reference signal and thus produces â€Å"Reference Spur† [20]. 2.5.4 Charge Pump Leakage Current When the CP output from the synthesizer is programmed to the high impedance state, in practice there should not be any current flow. But in practical some leakage current flows in the circuit and this is known as â€Å"charge pump leakage current† [20]. 2.6 Applications of PLL The demand of the PLL circuit increases day by day because of its wide application in the area of electronics, communication and instrumentation. The recent applications of the PLL circuits are in memories, microprocessors, hard disk drive electronics, RF and wireless transceivers, clock recovery circuits on microcontroller boards and optical fiber receivers. Some of the PLL applications are mentioned below. 1. Frequency Synthesis A frequency synthesizer is an electronic system for generating a range of frequencies from a single fixed time base or oscillator. 2. Clock Generation Many electronic systems include processors of various sorts that operate at hundreds of megahertz. Typically, the clocks supplied to these processors come from clock generator PLLs, which multiply a lower-frequency reference clock (usually 50 or 100 MHz) up to the operating frequency of the processor. The multiplication factor can be quite large in cases where the operating frequency is multiple GHz and the reference crystal is just tens or hundreds of megahertz. 3. Carrier Recovery (Clock Recovery) Some data streams, especially high-speed serial data streams (such as the raw stream of data from the magnetic head of a disk drive), are sent without an accompanying clock. The receiver generates a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data stream with a PLL. This process is referred to as clock recovery. 4. SkewReduction This is one of the very popular and earliest uses of PLL. Suppose synchronous pair of data and clock lines enter a large digital chip. Since clock typically drives a large number of transistors and logic interconnects, it is first applied to large buffer. Thus, the clock distributed on chip may suffer from substantial skew with respect to data. This is an undesirable effect which reduces the timing budget for on-chip operations. 5. Jitter and Noise Reduction One desirable property of all PLLs is that the reference and feedback clock edges be brought into very close alignment. The average difference in time between the phases of the two signals when the PLL has achieved lock is called the static phase offset. The variance between these phases is called tracking jitter. Ideally, the static phase offset should be zero, and the tracking jitter should be as low as possible. CHAPTER 3 CONVEX OPTIMIZATION OF VCO IN PLL 3.1 What is an optimization technique? Optimization technique is nothing but the finding of the action that optimizes i.e. minimizes or maximizes the result of the objective function. Optimization technique is applied to the circuits aiming at finding out the optimized circuit design parameter to achieve either the best performance or the desired performance. Optimization techniques are a set of most powerful tools that are used in efficiently handling the design resources and there by achieve the best result. Mainly optimization techniques are applied to the circuit for the selection of the component values, devices sizes, and value of the voltage or current source. 3.2 Types of circuit optimization method There are mainly four types of circuit optimization methods exist. They are Classical optimization Knowledge based optimization Global optimization method Convex optimization and geometric programming 3.2.1 Classical Optimization Methods: In case of analog circuit CAD, classical optimization methods [21], such as steepest descent, sequential quadratic programming, and Lagrange multiplier methods are mainly used. These methods are used with more complicated circuit models, including even full SPICE simulations in each iteration. This method can handle a wide variety of problem. For this there is a need of a set of performance measures and computation of one or more derivatives. The main disadvantage of the classical optimization methods is that the global optimal solution is not possible. This method fails to find a feasible design even one exist. This method gives only the local minima instead of global solution. Since many different initial designs are considered to get the global optimization, the method becomes slower. Because of the human intervention (to give â€Å"good† initial designs), the method becomes less automated. The classical methods become slow if complex models are used. 3.2.2 Knowledge-Based Methods: Knowledge-based and expert-systems methods such as genetic algorithm or evolution systems, systems based on Fuzzy logic, and heuristics-based systems have also been widely used in analog circuit CAD [21]. In case of knowledge based methods, there are few limitations on the types of problems, specifications, and performance measures that are to be considered. These methods do not require the computation of the derivatives. This is not possible to find a global optimal design solution using these methods. The final design is decided on the basis of the initial design chosen and the algorithm parameters. The disadvantage of the knowledge based methods is that they simply fail to find a feasible solution even when one may exist. There is a need of human intervention during the design and the training process. 3.2.3 Global Optimization Methods: Global optimization methods such as branch and bound and simulated annealing are also used in analog circuit design [21]. These methods are guaranteed to find the global optimal design solution. The global optimal design is determined by the branch and bound methods unambiguously. In each iteration, a suboptimal feasible design and also a lower bound on the achievable performance is maintained by this method. This enables the algorithm to terminate non-heuristically, i.e., with complete confidence that the global design has been found within a given tolerance. The branch and bound method is extremely slow, with computation growing exponentially with problem size. The trapping in a locally optimal design can be avoided by using simulated annealing (SA). This method can compute the global optimal solution but not guaranteed. Since there is no real-time lower bound is available, so termination is heuristic. This method can also handle a wide variety of performance indices and objects. T he main advantage of SA is that it handles the continuous variables and discrete variables problems efficiently and reduces the chances of getting a non-globally optimal design. The only problem with this method is that it is very slow and can not guarantee a global optimal solution. 3.2.4 Convex Optimization and Geometric Programming Methods: Geometric programming methods are special optimization problems in which the objective and constraint functions are all convex [22-24]. Convex optimization technique can solve the problems having a large number of variables and constraints very efficiently [22]. The main advantage of this method for which people generally adopt is that the method gives the global solution. Infeasibility is unambiguously detected. Since a lower bound on the achievable performance is given, so the method uses a completely non- heuristic stopping criterion. 3.3 Geometric programming and convex optimization Geometric programming is a special type of optimization technique in which all the objective must be convex. Before applying this technique it has to confirm that whether the given problem is convex optimization problem or not. Convex optimization problem means the problem of minimizing a convex function subject to convex inequality constraints and linear equality constraints. In IC integration convex optimization and geometric programming has become a more efficient computational tool for optimization purpose. This method has an ability to handle thousands of variables and constraints and solve efficiently. The main advantage of convex optimization technique is that it gives the global optimized value and the robust design. The fact that geometric programs can be solved very efficiently has a number of practical consequences. For example, the method can be used to simultaneously optimize the design of a large number of circuits in a single large mixed-mode integrated circuit. The de signs of the individual circuits are coupled by constraints on total power and area, and by various parameters that affect the circuit coupling such as input capacitance, output resistance, etc. Convex optimization is used to find out the optimized value of these parameter and sizing of the devices in the circuit [25]. Another application is to use the efficiency to obtain robust designs i.e., designs that are guaranteed to meet a set of specifications over a variety of processes or technology parameter values. This is done by simply replicating the specifications with a (possibly large) number of representative process parameters, which is practical only because geometric programs with thousands of constraints are readily solved. A real valued function fx defined on an interval (space) is called convex if ftx1+1-tx2≠¤tfx1+1-tfx2 (11) For every t,0 In the Figure 3.1 function fx is represented as a convex function on an interval. The convex optimization problem is in the form of minimize f0x Subjected to fix≠¤1 , i=1, 2, 3†¦, m gix=1 , i=1, 2, 3†¦, p xi>1 , i=1, 2, 3†¦, n Where fix is a posynomial function gix is a monomial function Let x1,x2†¦Ã¢â‚¬ ¦xn be n real positive variables. We can denote the vector (xi,xi†¦Ã¢â‚¬ ¦.xi) of these variables asx. A function f is called a posynomial function of x if it has the form fix1,x2†¦Ã¢â‚¬ ¦xn=k=1tCkx1ÃŽ ±1kx2ÃŽ ±2k†¦..xnÃŽ ±nk (12) Where Cj≠¥0 and ÃŽ ±ij à Ã‚ µ R. The coefficients Cj must be nonnegative but the exponents ÃŽ ±ij can be any real numbers including negative or fractional. When there is exactly one nonzero term in the sum i.e. t=1 and C1>0, we call f is a monomial function. 3.3.1 Advantages:  § Handle thousands of variables and constraints and solve efficiently.  § Global optimization can be obtained. 3.3.2 Disadvantages: * Strictly limited to types of problems, performance specification and objectives that can be handled. 3.4 Optimization of the VCO circuit In my earlier design of the VCO circuit, the sizes of all the five inverter stages are same. Now the convex optimization technique is applied to find out the optimal scaling ratio of the different inverter stages to get the optimal design with a better performance. There are 5 inverter stages and the design has to give a delay of 100ps. The load capacitance of the VCO circuit is 65 fF. All these design constraints are formulated and applied to the convex optimization technique. Mainly optimization techniques are applied for selection of component values and transistor sizing. In this work I have used the geometric programming technique to find out the optimized scaling ratio of the different stages in CSVCO to meet the desired center frequency with lesser deviation. Let xi is the scaling ration of the ith stage, CL is the load capacitance, and D is the total delay of the inverter stages then optimization problem is in the form of Minimize sum (xi) Subjected to CL≠¤CLmax D≠¤Dmax Where CLmax and Dmax are required design parameters and has a constant value. CHAPTER 4 DESIGN AND SYNTHESIS OF PLL 4.1 Design Environment The schematic level design entry of the circuits is carried out in the CADENCE Virtuoso Analog Design Environment. The layout of the PLL is designed in Virtuoso XL using GPDK090 library. In order to analyze the performances, these circuits are simulated in the Spectre simulator of CADENCE tool. Different performance indices such as phase noise, power consumption and lock time are measured in this environment. Transient, parametric sweep and phase noise analyses are carried out in this work to find out the performances of the circuit. The optimization of the current starved VCO circuit, the scale factor for transistor sizing is found out using the MATLAB environment. 4.2 Design Procedure 4.2.1 VCO Design Since VCO is the heart of the whole PLL system, it should be designed in a proper manner. The design steps for the current starved VCO are as follows. Step 1 Find the value of the propagation delay for each stage of the inverter in the VCO circuit using the following equation. Ï„p=1Nf (13) Where Ï„p= Ï„phl= Ï„plh= half of the propagation delay time of the inverter N= no of inverter stages f= required center frequency of oscillation Step 2 Find the WL ratio for the transistors in the different inverter stages using the equation in below. WL n=CloadÏ„phl µnCoxVdd-VT,n2VT,nVdd-VT,n+ln4Vdd-VT,nVdd-1 (14) WL p=CloadÏ„plh µpCoxVdd-VT,p2VT,pVdd-VT,p+ln4Vdd-VT,pVdd-1 (15) Step 3 After finding the WL ratio, find the values for W and L. Step 4 Find the value of the total capacitance form the expression Ctot=52Cox(LpWp+LnWn) (16) Where Cox is the oxide capacitance Lp,Wp,Ln,Wn is the width and length of the PMOS and NMOS transistors in the inverter stages. Step 5 Calculate the value of drain current for the center frequency which is given by IDcenter=NCtotVddf (17) Step 6 Find the WL ratio for the current starving transistors in the circuit from the drain current expression which is represented as WL n=2Ãâ€"IDcenter µnCoxVgs-VT,n2 (18) Similarly WL p=2.5Ãâ€"WL n (19) 4.2.2 Design of Phase Locked Loop The value of the charge pump current and the component parameters of the loop filter play a major role in the design of the phase locked loop circuit. The value of the lock time mainly depends upon these parameters. So while designing the circuit proper care should be taken in calculating these parameters. For the given values of reference(Fref) and output frequency(Fout) as well as the lock in range, the following steps to be carried out in designing the filter circuit. Step 1 Find the value of the divider circuit to be used which is given by n=FoutFref (20) Step 2 Find the value of the natural frequency (ωn) from the lock in range as given below lock in range=2Ãâ€"ÃŽ ¾Ãƒâ€"ωn (21) Step 3 Find the value of the charge pump gain (KPDI) from the charge pump current used in the circuit which is given by KPDI=Ipump2Ï€ (Amps/radian) (22) Step 4 Find the value of the gain of the VCO (Kvco) circuit from the characteristics curve using the following expression. Kvco=fmax-fminVmax-Vmin (Hz/V) (23) Step 5 Find the values of the loop filter component parameters using the following expressions. C1=KPDIÃâ€"KvcoNωn2 (24) C2=C110 (25) R=2ÃŽ ¾Ãâ€°nC1 (26) 4.3 Design Specifications and Parameters 4.3.1 VCO Design Specification The current starved VCO design specifications are mentioned in the following table. Table 1 VCO design specifications 4.3.2 VCO Design Parameters Table 2 List of design parameters of the CSVCO circuit 4.3.3 PLL Design Parameters The whole PLL system design specifications and parameters are shown in the Table 3. Parameter Value Reference frequency((Fref) 500 MHz output frequency(Fout) 1 GHz Lock in range 100 MHz

Ethnics and Heritage Destroyed George in Gloria Naylor’s Mama Day :: Gloria Naylor Mama Day Essays

Ethnics and Heritage Destroyed George in Gloria Naylor’s Mama Day It has been said before that opposites attract when it comes to love. In Gloria Naylor’s Mama Day, two people who would seemingly never end up together somehow find a way to form a relationship that eventually leads to a marriage. George and Cocoa, the two lovers featured in this book, come from backgrounds that could not be more unlike the other. How they end up falling in love is close to a miracle, but because of their huge difference in background, they bring to each other what they wish they could have in themselves. While George is a man who comes from the diverse and strictly governed big city atmosphere of New York, Ophelia is a woman who was raised on the island of Willow Springs which is inhabited by descendants of slaves and is subject to racism and disregard for normal conduct in society. New York is a place where science and facts control the decisions of life; Willow Springs has many rituals based on magic and superstition. Because the two locations are so incre dibly opposite from one another, it is difficult for George to believe in anything that Cocoa was raised on. However, in order for George to get Mama Day’s approval, he must believe and understand magic as it exists in Willow Springs both in its physical form and as a form of belief. The biggest influence of magic on the island of Willow Springs is Mama Day. A descendant of the legendary Sapphira Wade, Mama Day is said to have convinced her master to give the land that is Willow Springs to the slaves, for which she â€Å"†¦bore him seven sons in less than a thousand days, to put a dagger through his kidney and escape the hangman’ noose, laughing in a burst of flames.† (Naylor 3) The influence of Sapphira’s magic is carried over into Mama Day, as it is said that she could, â€Å"†¦walk through a lighting storm without being touched; grab a bolt of lightning in her hand; use the heat of lightning to start the kindling going under the medicine pot.† (Naylor 3) For a rational minded person like George, this and some of the other traditions can be hard to accept. One such example of George’s ideas of normal human behavior clashing with Mama Day’s occurs when Mama Day and Grandmother Abigail give the married couple a quilt made entirely of articles of clothing from past generations.

India and Pakistan: Most Different Systems

It is a cardinal truth that one of the most important factors in the political environment of the Asiatic region is the relationship between India and Pakistan. The system analysis with regard to India and Pakistan is a most interesting affair for an obvious reason. It shows how a people who had lived together for centuries can drift apart on communal question. Not only that, it also shows that due to differences in political culture the two states have, in spite of an equal start, chosen two divergent ways. As such, their fundamental differences have become clearly visible and practically speaking, it is very difficult, if not impossible to bridge the gulf. Particularly, their conflict has, in the meanwhile, turned this Asiatic region into a storm centre which may at any time trigger off a nuclear holocaust. Above all, this political tension has merged with global politics and, hence, the problem has become more acute. Before August 15, 1947, India was a unified state. The two dominions – India and Pakistan – came into being as separate states on that very day as a result of communal frenzy and blood-strained riots. It is a significant fact that the British rule was introduced in India by overthrowing the Muslim rulers and, hence, the Muslim community had a bitter hatred of the British. This hatred soon turned into an enmity with the western culture as well as their science and literature. But the Hindus accepted English and, thus, soon they were acquainted with the western culture and their thoughts – specially the concepts of liberty. As such, political consciousness grew up rapidly and in 1885, the Congress came into being as a national organization for political agitation. Though it was a secular entity and many Muslims joined it with a genuine eagerness, some Muslim leaders dubbed it as a Hindu organization and Sayid Ahmed, in particular, taught the Muslims that their interests were different and even at cross purposes. Thus, a counter movement came to the fore, swearing loyalty to the British. â€Å"The British also pulled strings behind the scene† (De, 103). In this way, the British authorities pursued the ‘Divide and Rule’ policy for its own interests and, thus, the gulf began to enlarge. With the British encouragement, the Muslim League was formed in 1906 for acting as a counterpoise for the Congress. Lord Dufferin, the Viceroy, once observed that ‘fifty millions of men were themselves a nation and a very powerful nation’. Similarly, Lord Salisbury, the Secretary of state for India announced that ‘it would be impossible for England to hand over the Indian Muslims to the tender mercies of hostile majority’. The British government was, thus, sowing the seeds of Pakistan more than half a century before it was actually born (Chopra, 16). But the elections of 1937 under the government of India Act hastened the crisis. While the Congress captured power in eight provinces, the league was totally disillusioned. The poor election results convinced Jinnah, the League-leader, that the only way to counteract the Congress was to inflame communal feelings among the Muslims (Sen, 263). Soon, in 1940, the League passed the Pakistan resolution for a separate state (Moon, 41). The rift soon reached the boiling point. The differences bitterly came up during the Cripps Mission and Cabinet Mission. Jinnah called for the ‘Direct Action Day’ on 16th August 1946 which resulted in a terrible blood bath. Soon an interim cabinet was formed – but it was torpedoed by the League Ministers (Bose, 135). It was, thus, realized that the two communities would not be able to live together – on August 15, 1947, two Dominions came up after a partition. Basic Differences Though both India and Pakistan had an equal start, the differences have become discernible which are discussed hereunder as follows: Political: Constitutional India has adopted a democratic system in which the actual power resides on the people. The central and provincial cabinets are, under Art 75 (2) and   Art 164 (1), responsible to the Lok Sabha and local Assembly respectively, which are composed by popular election. Moreover, Art 326 has granted the right to vote to each person irrespective of class, creed, religion etc. after reaching the age of 18. Thus, this is a dynamic representative democracy (Basu, 23). However, soon after the birth of Pakistan, it came under military dictatorship. Though on occasions, civil governments came to power, it is primarily a military system virtually from 1969 (Agarwal, 422). Foreign Policy: India has adopted the principal of non-alignment in its foreign policy when in the post war period most of the states joined either of the two power blocs, India, along with a few other nations, adopted the policy of equidistance from them. It means the independence of action. India’s foreign policy does not allow herself to follow a previously defined path. This independence of action enables India to judge each issue in its own merits and without any prejudice (Keswani, 512). But, in order to enlist American support on the Kashmir issue, Pakistan, soon after its birth, joined the American bloc. Pakistan sought artificial strength by her alliance with America and through SEATO and the Baghdad pact (Khanna, 78). But, curiously, after the Sino-Indian war of 1962 (when America came forward with its men, machines and money to save India from a probable Chinese destruction), Pakistan entered into a friendly treaty with China, a stalwart of communist camp. It means, unmistakably, that Pakistan has no consistency in its foreign policy. Most surprisingly, while Pakistan resorted to a friendly relation with America, it is also maintaining (at least reportedly) a positive relation with the Middle Eastern states – some of whom are even arch rivals of the United Sates. Its main consideration is enmity with India. Party System India had, initially, a ‘one party dominant system’ (Morris-Jones, 215). However, with its gradual eclipse, coalition politics has spread over the country. It obviously implies some alliances and compromises among the leaders of various parties for directing the political affairs. But, Pakistan is dominated not by the political leaders, but by the military Generals. One General has captured power by removing another through military coup. Thus, politics has been dominated there by militarism and an understanding between the Government and the Opposition has been a rare affair. Religious India has accepted the principle of secularism which implies governmental impartiality in religious affairs. Its Preamble has granted ‘liberty of thoughts, expressions, faith, beliefs and worship’. Moreover, Articles 25, 26, 27 and 28 have been the sheet anchor secularism (Johari, 394). Above all, by the 42nd amendment of 1976, it has inserted the term ‘Secular’ in the Preamble. Thus, religious tolerance is the basic feature of the Indian system. But, Pakistan is an Islamic country which has accepted Islam as the state religion. However, on the morning of July 13, 1947, Jinnah declared Minorities, to whichever community they may belong, will be safeguarded. Their religion, or faith or belief will be protected in every way possible. Their life and property will be secure. There will be no interference of any kind with their freedom of worship. They will have their protection with regard to their religion, their faith, their life, their property, and their culture. They will be, in all respects, citizens of Pakistan without any distinction of caste or color, religion or creed. (qtd. in Kauba 89) However, being a typical Islamic state, Pakistan accepted Islam as the state-religion and, in most cases, knows no tolerance of other faiths. The laws are based on ‘Sheriyat’ which is claimed to be derived from the sacred Quran. In such states, ‘Ulemas’ and ‘Imams’ guide the social and religious life and a sharp discrimination exists between the Muslims and the other subjects living within the state. People belonging to other creeds such as the Christians, the Buddhists, and the Hindus etc. are looked down upon and seldom treated with dignity and honor. The public sectors hardly tolerate any of these creeds at higher designation in the organizational hierarchy. Moreover, the educational syllabus is over burdened with religious lessons instead of practical industrial requirements. Economic Economic systems of the two countries are quite different. India adopted a unique blend of the ideals of socialistic and capitalistic economies. Since the early 1950s it has been proceeding towards economies of development through Five Year Plans (Bhattacharya, 1). It is thus a planned economy with big private sectors. Since its globalization and liberalization policies of 1992, giant multinationals throughout the world has shown serious interest on the Indian market. Resultantly, India has emerged as the fastest growing and the fourth largest economy of the world (Paul, 215). However, Pakistan has adopted purely a capitalistic economy where planning has no place at all. Due to its religious intolerance, political disorders, and dictatorial environment the foreign companies are often too much hesitant to invest in that market. Natural Resources India is much richer in natural resources. It has a vast territory where different types of agricultural crops are produced and mineral resources are harvested. In comparison, Pakistan is surly poor. Rice and wheat are the main crops. It has some mineral wealth, textiles, jute and tea – (Clement, 64). Some Problems Problems Both India and Pakistan are disturbed by some acute problem. After the gradual erosion of the Congress, a multi – party chaos has gripped India and it has evoked political atmosphere. There are nearly 350 political parties and most of them are leased upon narrow opportunism. Naturally, the task of nation-building has been cast down by such trifling conflicts. Economically also, India is facing a crisis. In spite of planned endeavor for five decades, a gross disparity of income and wealth has been. Communalism is also a formidable problem. Hindu-Muslim conflict has become a common affair and there may be riots just for anything or nothing (Das, 400) In foreign affairs too, some problems seem to be insoluble. With America and China, two super-powers, its relationship is less than normal. Pakistan, its neighbor, is the worst enemy and, Bangladesh, for which it fought in 1971, has drifted far away. Pakistan is, similarly, disturbed with some crucial problems. The conflict between the Siyas and Sunnis often result in severe blow-birth. Moreover, some political parties often agitate against the autocratic Government and it ultimately results in awful bloodshed. But, above all, while there is a large-scale poverty, a considerable part of the national income is to be diverted to the war-preparation. In fact, the Government has to encourage a frenzied bellicosity in its relations with India in order to mobilize public support. In 1949, Pakistan was pushed back in Kashmir and in 1951, 1965 and 1971 it suffered a terrible defeat by India. So the Pak-rulers have been forced to adopt a war-economy, though the national poverty badly needs a peace-time growth-program. Nuclear Preparation   It is interesting to note that fear of war has compelled both India and Pakistan to enter into a race of armament. Thus, through a prolonged endeavor both of them have now become atomic power. But, it is well known that fear of war increases armament and increase of armament increases the fear of war. In this way, their rivalry has ushered in an era of permanent panic. If a war actually breaks out, it would be profitable to none, because the nuclear bombardment would surely bring about a total catastrophe for not only the belligerents but also for the entire region. For this reason, some sort of understanding is urgently necessary. Of course, Kashmir is the bone of contention between them and none is prepared to give up its claim over this strategic spot. But, unless some compromise is reached, the conflict of Kashmir might one day, obliterate the both of them from the global map. Conclusion But, by any means, they must find out a way towards the lasting peace. It is interesting to note that though Germany was divided into two parts after the Second World War. However, they have, after five decades, merged together. In this sense, India and Pakistan cannot, perhaps in the near future, mingle together in this way. But, for realistic reasons, they must come nearer and build up a workable relationship. Of course, Kashmir has stood up as the stumbling obstacle. But mutual war and conflicts can never bring about a peaceful solution. Only an understanding on the basis of ‘give and take’ policy can solve the problem which has thrice dragged them into armed conflict. Particularly, Pakistan must remember that it has no legal claim over Kashmir. Before the partition of undivided India, the Instrument of Accession offered the Princely states the right to join either of the two Dominions. The king of Kashmir (Hari Sing) duly signed a treaty with India for joining it. (Mahajan, 343). The portion of Kashmir (Pak occupied Kashmir) which is now under Pakistan’s control, was captured only by illegal infiltration by several terrorist groups. Hence, it is beyond any iota of doubt that history can go a long way in setting the problem to the right perspective. Works Cited Agarwal, R.G. Political Theory, Chandra Books, Allahabad, 1996, 422 Basu, D.D. Introduction to the Constitution of India, Prentice Hall, 1978, 23 Bhattacharya, D.C. India’s Five Year Plans, Joy Library, Calcutta, 1996, 1 Bose, N.S. Indian National Movement, Pharma K.L.M. Pvt. Ltd, 1974, 135 Chauba, K.L. India and Pakistan, Raj Kamal Publications, New Delhi, 1948, 49 Chopra, P.N. India’s Struggle for Freedom, Publications Division, 1984, 16 Das, H.H. India: Democratic Government and Politics, Himalaya Publications, New Delhi, 1991, 400 De, B. Freedom Struggle, Publications Division, New Delhi, 1992, 103 Johari, J.C. Indian Government and Politics, Vishal Publishing House, New Delhi, 394 Kauba, K.L. Inside Pakistan, Raj Kamal Publications, New Delhi, 1948, 89 Keswani, K.B. International Relations, Himalaya Publishing, Mumbai, 1996, 512 Khanna, V.H. Foreign policy of India, Vikas Publishing, Chennai, 1997, 78 Mahajan, V.D. The Constitution of India, Modern Books, New Delhi, 1979, 343 Moon, P. Divide and Quit, Modern Books, Mumbai, 41 Morris-Jones, W.H. Government and Politics of India, B.I. Publications, New Delhi, 1979, 215 Sen, S.N. History of Freedom Movement in India, New Age Publications, 1978, 263

Doubt in Hamlet - 1267 Words

‘Her death was doubtful.’ Analyse the theme of doubt in Hamlet. In Shakespeare’s play Hamlet, doubt is one of the most important themes. In fact, the whole play is based on the story of a ghost who claims to be Hamlet’s father, and nobody can be sure if what he says is the truth. In this essay, I am going to focus on the theme of doubt throughout the play. I will first speak about the opening scene, and then I will talk about the ghost, which is a supernatural element used by Shakespeare to create doubt in the play. I will also analyse the passage in which Hamlet declares his love to Ophelia. Finally, I will briefly discuss Hamlet’s sanity. What happens in the opening scene is very relevant and foreshadows the atmosphere of the whole†¦show more content†¦I think that the last scene of the first act is one of the most important ones because it is when the ghost demands Hamlet to â€Å"[r]evenge his [father] foul and most unnatural murder† (1.5.25). By asking revenge, the ghost introduces here the main plot of the play, which is going to be based on that revelation. We do not know if Hamlet can trust the phantom’s accusations, if the ghost accuses Claudius because he has proof of Claudius’s guilt or just because he is deducing. Hamlet cannot be sure of any of those questions, and I think that it is this doubt introduced by the ghost that makes Hamlet incapable of action and revenge. The plot of the play focuses on the one hand on the impossibility to know the truth, and on the other hand on the necessity to know the truth to act with justice and with honour. As D.G. James says in his essay, â€Å"[c]onscience requires that we do is right; but then, what is right or wrong in these circumstances?† We can thus say that Hamlet is right to hesitate. It is only in the second act that Hamlet begins to doubt, and begins to think that â€Å"[t]he spirit that [he] ha[s] seen/ May be the devil† (2.2.575-6). When Hamlet realizes that it â€Å"may be a deceiving spirit†, he decides to stage that play to trap Claudius. But â€Å"when his guilt was proved beyond any doubt, Hamlet still did not kill him; he left him alone, giving a reason, plausible enough in Hamlet’s eyes, in the eyes of his audience, and in our eyes [†¦]† (Hattaway, p83). As I said before, theShow MoreRelatedDoubt in Hamlet1256 Words   |  6 PagesAnalyse the theme of doubt in Hamlet. In Shakespeare’s play Hamlet, doubt is one of the most important themes. In fact, the whole play is based on the story of a ghost who claims to be Hamlet’s father, and nobody can be sure if what he says is the truth. In this essay, I am going to focus on the theme of doubt throughout the play. I will first speak about the opening scene, and then I will talk about the ghost, which is a supernatural element used by Shakespeare to create doubt in the play. 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